37.10.5 System Clock

Table 37-14. System Clock Timing Characteristics
Symbol Description Min. Typ. ✝ Max. Unit Conditions
fCLK_MAIN Main clock frequency(1,2) — — 24 MHz
fCY Instruction clock frequency — fCLK_MAIN — MHz
TCY Instruction period(3) 41.6 1/fCY — ns

✝ Data found in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested.

Note:
  1. The main clock frequency (CLK_MAIN) is configured by the Clock Select (CLKSEL) bit field, as described in the CLKCTRL - Clock Controller section.
  2. The main clock frequency (CLK_MAIN) must meet the voltage requirements defined in 37.3 Standard Operating Conditions.
  3. The Instruction Cycle Period (TCY) is identical to the input oscillator time base period. Exceeding these limits may result in incorrect code execution and/or higher-than-expected current consumption. All devices are tested to operate at ‘min’ values with an external clock applied to the EXTCLK pin. When using an external clock input, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices.