29.5.8 LUT n Control A

Name: LUTnCTRLA
Offset: 0x08 + n*0x04 [n=0..5]
Reset: 0x00
Property: Enable-Protected

Bit 76543210 
 EDGEDETOUTENFILTSEL[1:0]CLKSRC[2:0]ENABLE 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 7 – EDGEDET Edge Detection

ValueDescription
0Edge detector is disabled
1Edge detector is enabled

Bit 6 – OUTEN Output Enable

This bit enables the LUT output to the LUTn OUT pin. When written to ‘1’, the pin configuration of the PORT I/O-Controller is overridden.
ValueDescription
0Output to pin disabled
1Output to pin enabled

Bits 5:4 – FILTSEL[1:0] Filter Selection

These bits select the LUT output filter options.

ValueNameDescription
0x0DISABLEFilter disabled
0x1SYNCHSynchronizer enabled
0x2FILTERFilter enabled
0x3-Reserved

Bits 3:1 – CLKSRC[2:0] Clock Source Selection

This bit selects between various clock sources to be used as the clock (CLK_LUTn) for an LUT.

The CLK_LUTn of the even LUT is used for clocking the sequencer of an LUT pair.

ValueInput SourceDescription
0x0CLKPERCLK_PER is clocking the LUT
0x1LUTn-TRUTHSEL[2]LUTn-TRUTHSEL[2] is clocking the LUTn
0x2-Reserved
0x3-Reserved
0x4OSCHFInternal high-frequency oscillator before prescaler is clocking LUT
0x5OSC32KInternal 32.786 kHz oscillator
0x6OSC1KInternal 32.768 kHz oscillator divided by 32
0x07-Reserved

Bit 0 – ENABLE LUT Enable

ValueDescription
0The LUT is disabled
1The LUT is enabled