10.5.3 Status
| Name: | STATUS |
| Offset: | 0x02 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERROR[2:0] | EEBUSY | FBUSY | |||||||
| Access | R/W | R/W | R/W | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bits 6:4 – ERROR[2:0] Error Code
Error code bit field reports the status of the last programming operation.
INVALIDCMD and WRITEPROTECT are cleared
only if/whenthe operation that caused the error is followed by a legal one. If
CMDCOLLISION error occurs, then any new programming
operation is ignored, until the error is cleared. Ensure no programming
operation is ongoing (see FBUSY and EEBUSY flags) before clearing this error,
otherwise the error will be reported once more.
The Error Code bit field can be cleared by writing ‘0’ to it.
Note: Rules for error/halting:
- If changing command while
programming is ongoing, then
CMDCOLLISIONerror is set. - If ERROR =
CMDCOLLISION, then the programming operation is ignored. - If accessing (read/write) while NVM section is busy, then the CPU is halted.
| Value | Name | Description |
|---|---|---|
| 0x0 | NONE | No error |
| 0x1 | INVALIDCMD | The selected command is not supported |
| 0x2 | WRITEPROTECT | Attempt to write a section that is protected |
| 0x3 | CMDCOLLISION | A new write/erase command was selected while a write/erase command is already ongoing |
| Other | — | Reserved |
Bit 1 – EEBUSY EEPROM Busy
1’ when an EEPROM programming operation is
ongoing.Bit 0 – FBUSY Flash Busy
1’ when a Flash programming operation is
ongoing.