29.2.2.1 CCL Input Selection MUX

The following peripherals outputs are available as inputs into the CCL LUT.


Value	Input source	INSEL0[3:0]	INSEL1[3:0]	INSEL2[3:0]
`0x00`	MASK	None
`0x01`	FEEDBACK	LUTn
`0x02`	LINK	LUT[n+1]
`0x03`	EVENTA	EVENTA
`0x04`	EVENTB	EVENTB
`0x05`	IO	IN0	IN1	IN2
`0x06`	AC	AC0 OUT	AC1 OUT	AC2 OUT
`0x07`	ZCD	ZCD0 OUT	ZCD1 OUT	ZCD2 OUT
`0x08`	USART	USART0 TXD	USART1 TXD	USART2 TXD
`0x09`	SPI	SPI0 MOSI	SPI0 MOSI	SPI0 SCK
`0x0A`	TCA0	WO0	WO1	WO2
`0x0B`	TCA1	WO0	WO1	WO2
`0x0C`	TCB	TCB0 WO	TCB1 WO	TCB2 WO
`0x0D`	TCD0	WOA	WOB	WOC
`0x0E-0x0F`	Reserved

Note:

SPI connections to the CCL work only in host SPI mode
USART connections to the CCL work only in asynchronous/synchronous USART host mode

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