3 Description

The AT34C04 provides 4,096 bits of Serial Electrically Erasable and Programmable Read-Only Memory (EEPROM) organized as 512 words of 8 bits each. The device’s cascading feature allows up to eight devices to share a common two‑wire bus.

The Serial EEPROM operation is tailored specifically for DRAM memory modules with Serial Presence Detect (SPD) to store a module’s vital product data such as the module’s size, speed, voltage, data width and timing parameters.

The AT34C04 is protocol compatible with the legacy JEDEC EE1002 specification (2-Kbit) devices enabling the AT34C04 to be utilized in legacy applications without any software changes. The device is designed to respond to specific software commands that allow users to identify and set which half of the memory the internal address counter is located. This special page addressing method to select the upper or lower half of the Serial EEPROM is what facilitates legacy compatibility. However, there is one exception to the legacy compatibility as the AT34C04 does not support the Permanent Write Protection feature.

Additionally, the AT34C04 incorporates a Reversible Software Write Protection (RSWP) feature enabling the capability to selectively write protect any or all of the four 128-byte quadrants. Once the RSWP is set, it can only be reversed by sending a specific software command sequence.

The AT34C04 supports the industry standard two-wire I²C Fast-Mode Plus (FM+) serial interface allowing device communication to operate at up to 1 MHz. A bus timeout feature is supported to help prevent system lock-ups. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. The device is available in space-saving 8- lead SOIC, 8-lead TSSOP and 8-pad UDFN packages. All packages operate from 1.7V to 3.6V.