2.4.5 Master Mode 10-Bit Receive Sequence

The following steps highlight a typical 10-bit receive sequence:

  1. Software sets the SEN bit, master hardware generates a Start condition.
  2. Upon the completion of the Start condition, hardware sets SSPxIF.
  3. Software clears the SSPxIF bit.
  4. Software loads SSPxBUF with the 10-bit high address byte and R/W bit. In 10-bit Master Receive mode, the first time the high address byte is transmitted, the R/W bit value is ‘0’ (see Figure 2-12).
  5. The high address byte is shifted out on the SDA line until all eight bits have been transmitted.
  6. Master hardware clocks in the ACK value from the slave and copies the value into the ACKSTAT bit.
  7. Master hardware sets the SSPxIF bit. If the SSPxIE bit is also set, an interrupt is generated. SSPxIF must be cleared by software.
  8. Software loads SSPxBUF with the 10-bit low address byte.
  9. The low address byte is shifted out on the SDA line until all eight bits have been transmitted.
  10. Master hardware clocks in the ACK value from the slave and copies the value into the ACKSTAT bit.
  11. Master hardware sets the SSPxIF bit. If the SSPxIE bit is also set, an interrupt is generated. SSPxIF must be cleared by software.
  12. Software sets the RSEN bit, hardware issues a Restart condition.
  13. Software loads SSPxBUF with the 10-bit high address byte and R/W bit. This second stage of addressing in 10-bit Master Receive mode requires the R/W bit value to be ‘1’.
  14. The high address byte is shifted out on the SDA line until all eight bits have been transmitted.
  15. Master hardware clocks in the ACK value from the slave and copies the value into the ACKSTAT bit.
  16. Master hardware sets the SSPxIF bit. If the SSPxIE bit is also set, an interrupt is generated. SSPxIF must be cleared by software.
  17. Software sets the RCEN bit, and hardware clocks in a byte from the slave.
  18. After the eight falling clock edge, the byte is transferred from the SSPxSR and sets the SSPxIF and BF bits. RCEN is cleared by hardware.
  19. Software clears SSPxIF and reads the received byte from SSPxBUF, clearing the BF bit.
  20. Software clears the ACKDT bit and initiates an ACK sequence by setting the ACKEN bit.
  21. Master hardware transmits the ACK sequence.
  22. On the ninth falling clock edge, SSPxIF is set. Software must clear SSPxIF.
  23. Repeat steps 17 - 22 until all bytes have been received from the slave.
  24. Master software can end communication by performing one of the following:
    • Software sets the ACKDT bit and transmits a NACK sequence by setting the ACKEN bit.
    • Software sets the PEN bit and hardware transmits a Stop condition.
    • Software sets the RSEN bit and hardware issues a Restart condition.
Figure 2-12. I2C Master Mode Waveform (Reception, 10-bit Address)