2.2 I2C Master Mode Operation

Master mode is enabled by configuring the MSSP Mode Select (SSPM) bits and setting the MSSP Enable (SSPEN) bit. The SDA and SCL pins must be configured as inputs by setting the associated TRIS bits (TRISxy = 1). MSSP hardware will automatically override the TRIS controls when necessary to drive the pins low.

Master mode operation is supported by interrupt generation on the detection of certain events. The following events will cause the MSSP Interrupt Flag (SSPxIF) bit to be set:
  • Start condition detected
  • Stop condition detected
  • Data byte transmitted/received
  • Acknowledge sequence transmitted/received
  • Restart condition detected

The Start (S) and Stop (P) bits are cleared by a Reset event or when the MSSP module is disabled. Control of the bus may be taken when the Stop bit is set (P = 1) or when the bus is Idle.

Important:
  1. The MSSP module, when configured in I2C Master mode, does not allow queuing of events. For example, user software is not permitted to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the Write Collision Detect (WCOL) bit will be set, indicating that the write did not occur.
  2. Master mode suspends Start/Stop condition detection when transmitting the Start/Stop conditions by means of the SEN/PEN control bits. The SSPxIF bit is set at the end of the Start/Stop condition, when hardware clears the associated SEN/PEN control bit.

The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer typically begins with a Start condition and ends with a Stop condition. A Restart condition may be used in place of a Stop condition, if the master device wishes to hold the bus to continue communication with the same or other slave devices.

In Master Transmit mode, data is transmitted over the SDA line, while the clock is transmitted over the SCL line. The first byte transmitted by the master contains the 7-bit address, or upper byte of a 10-bit address, and the R/W bit. In Transmit mode, the R/W bit is clear (R/W = 0). Data is transmitted eight bits at a time, and after each byte has been sent, the master releases the clock line and waits for the reception of an Acknowledge sequence from the slave. Once the master has received all of the data it requests, it can issue a Stop condition to terminate transmission, or issue a Restart condition if it wishes to hold control of the bus.

In Master Receive mode, the first byte transmitted is the 7-bit address, or upper byte of the 10-bit address, and the R/W bit. In 7-bit Receive mode, the R/W bit is set (R/W = 1). In 10-bit Receive mode, the R/W bit contained in the first transmitted address byte is clear (R/W = 0). After the successful transmission of the upper and lower address bytes, the master issues a Restart condition and transmits the upper address byte again, this time with the R/W bit set (R/W = 1). In Receive mode, the master receives data over the SDA line, but continues to generate the clock signal over the SCL line. After the master receives each byte, it typically transmits an ACK sequence back to the slave. Once the master has received the final byte, it can respond with either an ACK or NACK sequence and issue either a Stop or Restart condition.