2.2.4 I2C Master Mode Repeated Start Condition Timing

A Repeated Start condition (see Figure 2-6) occurs when the Repeated Start Condition Enable (RSEN) bit is programmed high and the master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG, while SCL is high. After the BRG sample time has passed, SCL is asserted low. Following this, the RSEN bit will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out.

Important:
  1. If RSEN is programmed while any other event is in progress, it will not take effect.
  2. A bus collision during the Repeated Start condition occurs if:
    • SDA is sampled low when SCL goes from low-to-high.
    • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data ‘1’.
Figure 2-6. Repeated Start Condition Waveform