2.3.4 Master Mode 7-Bit Transmit Sequence

The following steps highlight a typical 7-bit transmit sequence:

1. Software sets the SEN bit, master hardware generates a Start condition.
2. Upon the completion of the Start condition, hardware sets SSPxIF.
3. Software clears the SSPxIF bit.
4. Software loads SSPxBUF with the 7-bit slave address and R/W bit. In Master Transmit mode, the R/W value is ‘0’.
5. The address is shifted out on the SDA pin until all eight bits have been transmitted.
6. Master hardware clocks in the ACK value from the slave and copies the value into the ACKSTAT bit.
7. Master hardware sets the SSPxIF bit. If the SSPxIE bit is also set, an interrupt is generated. SSPxIF must be cleared by software.
8. Software loads SSPxBUF with a data byte.
9. Data is shifted out until all eight bits have been transmitted.
10. Master hardware clocks in the ACK value from the slave and copies the value into the ACKSTAT bit.
11. On the ninth falling clock edge, SSPxIF is set by hardware. If SSPxIE is also set, an interrupt is generated. SSPxIF must be cleared in software.
12. Repeat steps 8 - 11 until all data has been transmitted.
13. Software generates a Stop or Restart condition by setting the PEN or RSEN bits, respectively. Once the Stop/Restart condition is complete, hardware sets SSPxIF.