2.3.5 Master Mode 10-Bit Transmit Sequence

The following steps highlight a typical 10-bit transmit sequence:

1. Software sets the SEN bit, master hardware generates a Start condition.
2. Upon the completion of the Start condition, hardware sets SSPxIF.
3. Software clears the SSPxIF bit.
4. Software loads SSPxBUF with the 10-bit high address byte and R/W bit. In 10-bit Master Transmit mode, the R/W bit value is ‘0’.
5. The high address byte is shifted out on the SDA line until all eight bits have been transmitted.
6. Master hardware clocks in the ACK value from the slave and copies the value into the ACKSTAT bit.
7. Master hardware sets the SSPxIF bit. If the SSPxIE bit is also set, an interrupt is generated. SSPxIF must be cleared by software.
8. Software loads SSPxBUF with the 10-bit low address byte.
9. The low address byte is shifted out on the SDA line until all eight bits have been transmitted.
10. Master hardware clocks in the ACK value from the slave and copies the value into the ACKSTAT bit.
11. Master hardware sets the SSPxIF bit. If the SSPxIE bit is also set, an interrupt is generated. SSPxIF must be cleared by software.
12. Software loads SSPxBUF with a data byte.
13. Data is shifted out until all eight bits have been transmitted.
14. Master hardware clocks in the ACK value from the slave and copies the value into the ACKSTAT bit.
15. On the ninth falling clock edge, SSPxIF is set by hardware. If SSPxIE is also set, an interrupt is generated. SSPxIF must be cleared in software.
16. Repeat steps 12 - 15 until all data has been transmitted.
17. Software generates a Stop or Restart condition by setting the PEN or RSEN bits, respectively. Once the Stop/Restart condition is complete, hardware sets SSPxIF.