35.4 Register Summary
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | CTRLA | 7:0 | ENABLE | |||||||
| 0x01 | DBGCTRL | 7:0 | DBGRUN | |||||||
| 0x02 | TIMEBASE | 7:0 | TIMEBASE[6:0] | |||||||
0x03 ... 0x0E | Reserved | |||||||||
| 0x0F | PWRCTRL | 7:0 | IRSEL | |||||||
| 0x10 | OP0CTRLA | 7:0 | RUNSTDBY | OUTMODE[1:0] | EVENTEN | ALWAYSON | ||||
| 0x11 | OP0STATUS | 7:0 | SETTLED | |||||||
| 0x12 | OP0RESMUX | 7:0 | MUXWIP[2:0] | MUXBOT[2:0] | MUXTOP[1:0] | |||||
| 0x13 | OP0INMUX | 7:0 | MUXNEG[2:0] | MUXPOS[2:0] | ||||||
| 0x14 | OP0SETTLE | 7:0 | SETTLE[6:0] | |||||||
| 0x15 | OP0CAL | 7:0 | CAL[7:0] | |||||||
0x16 ... 0x17 | Reserved | |||||||||
| 0x18 | OP1CTRLA | 7:0 | RUNSTDBY | OUTMODE[1:0] | EVENTEN | ALWAYSON | ||||
| 0x19 | OP1STATUS | 7:0 | SETTLED | |||||||
| 0x1A | OP1RESMUX | 7:0 | MUXWIP[2:0] | MUXBOT[2:0] | MUXTOP[1:0] | |||||
| 0x1B | OP1INMUX | 7:0 | MUXNEG[2:0] | MUXPOS[2:0] | ||||||
| 0x1C | OP1SETTLE | 7:0 | SETTLE[6:0] | |||||||
| 0x1D | OP1CAL | 7:0 | CAL[7:0] | |||||||
0x1E ... 0x1F | Reserved | |||||||||
| 0x20 | OP2CTRLA | 7:0 | RUNSTDBY | OUTMODE[1:0] | EVENTEN | ALWAYSON | ||||
| 0x21 | OP2STATUS | 7:0 | SETTLED | |||||||
| 0x22 | OP2RESMUX | 7:0 | MUXWIP[2:0] | MUXBOT[2:0] | MUXTOP[1:0] | |||||
| 0x23 | OP2INMUX | 7:0 | MUXNEG[2:0] | MUXPOS[2:0] | ||||||
| 0x24 | OP2SETTLE | 7:0 | SETTLE[6:0] | |||||||
| 0x25 | OP2CAL | 7:0 | CAL[7:0] | |||||||