3.1 Digital Signal Processor

A Digital Signal Processor (DSP) is used to perform speech and audio processing. The advanced speech features, such as AES and NR are inbuilt. To reduce nonlinear distortion and to help echo cancellation, an outgoing signal level to the speaker is monitored and adjusted to avoid saturation of speaker output or microphone input. In addition, adaptive filtering is applied to track the echo path impulse in response to provide echo free and full-duplex user experience.

The embedded noise reduction algorithm helps to extract clean speech signals from the noisy inputs captured by the microphones and improves mutual understanding in communication. The advanced audio features, such as multiband dynamic range control, parametric multiband equalizer, audio widening and virtual bass are inbuilt. The audio effect algorithms improve the user’s audio listening experience in terms of better-quality audio after audio signal processing.

Note: DSP parameters can be configured using the Config Tool.

The following figures illustrate the processing flow of speaker phone applications for speech and audio signal processing.

Note: LDAC is supported only in the IS2083BM-2L2 device.

The DSP core consists of three computational units (ALU, MAC, and Barrel Shifter), two data address generators, PMD-DMD bus exchanger, program sequencer, bi-directional serial ports (SPORT), DMA controller, interrupt controller, programmable I/O, on-chip program, and on-chip data memory.

The DSP memory subsystem defines the address ranges for the following addressable memory regions:

Program space
- 96 KB of Program RAM
- 12 KB of Patch RAM
- 64 KB of Coefficient RAM

Data space
- 96 KB of Data RAM

I/O Space
- Memory-mapped registers

The DSP core implements a modified Harvard architecture in which data memory stores data and program memory stores both instructions and data (coefficients).