3.1.3 PDMIC XDMAC Channel Initialization

A DMA channel from the XDMAC module is configured to transfer the converted data from the PDMIC interface to the main memory buffer. The code snippet given below configures the XDMAC channel 0 in a single block – Single Micro Block mode with a micro block length equal to 10*48000 (48-kHz sample rate for 10 seconds).

/* Enable peripheral clock for XDMAC0 */
PMC->PMC_PCER0 = (1u << ID_XDMAC0);

/* Read the interrupt status register to clear the interrupt flags */
temp = XDMAC0->XDMAC_CHID[0].XDMAC_CIS;

/* Set source address as PDMIC_CDR register */
XDMAC0->XDMAC_CHID[0].XDMAC_CSA = (uint32_t)&PDMIC->PDMIC_CDR;

/* Set destination address as starting address of audio buffer */
XDMAC0->XDMAC_CHID[0].XDMAC_CDA = (uint32_t)audio_data;

/* Set micro block length */
XDMAC0->XDMAC_CHID[0].XDMAC_CUBC = 10*48000;

/* Set DMA channel parameters */
XDMAC0->XDMAC_CHID[0].XDMAC_CC = XDMAC_CC_TYPE_PER_TRAN                                     
                                    | XDMAC_CC_MBSIZE_SINGLE
                                    | XDMAC_CC_DSYNC_PER2MEM                                    
                                    | XDMAC_CC_CSIZE_CHK_1
                                    | XDMAC_CC_DWIDTH_HALFWORD
                                    | XDMAC_CC_SIF_AHB_IF1
                                    | XDMAC_CC_DIF_AHB_IF0
                                    | XDMAC_CC_SAM_FIXED_AM
                                    | XDMAC_CC_DAM_INCREMENTED_AM
                                    | XDMAC_CC_PERID(50);

/* Set all registers related to descriptor to 0 */
XDMAC0->XDMAC_CHID[0].XDMAC_CNDC = 0;
XDMAC0->XDMAC_CHID[0].XDMAC_CBC = 0;
XDMAC0->XDMAC_CHID[0].XDMAC_CDS_MSP = 0;
XDMAC0->XDMAC_CHID[0].XDMAC_CSUS = 0;
XDMAC0->XDMAC_CHID[0].XDMAC_CDUS = 0;

The DMA channel source address is set to the PDMIC_CDR result data register, and the destination address is set to the start of the buffer. Here, "audio_data" is an array of type signed 16-bit integer and of size 10*48000. The transfer size is set to half-word with a fixed source address and a destination address incrementing for each transfer.

No descriptors are used for the transfer, so the XDMAC registers related to the descriptor configuration are set to zero.