3.1.4 PDMIC Initialization

The following code snippet initializes the PDMIC interface with its clock source set to Audio PLL through the PMC’s GCLK source.

/* Enable Audio PLL as source for PDMIC through GCLK */
PMC->PMC_PCR = PMC_PCR_PID(ID_PDMIC) 
                | PMC_PCR_GCKCSS_AUDIO_CLK 
                | PMC_PCR_CMD 
                | PMC_PCR_GCKDIV(7)
                | PMC_PCR_EN 
                | PMC_PCR_GCKEN;

/* Wait until GCLK is ready */
while (!(PMC->PMC_SR & PMC_SR_GCKRDY));

/* Perform software reset of PDMIC peripheral */
PDMIC->PDMIC_CR = PDMIC_CR_SWRST;

/* Select GCLK as clock source and set perscaler */
PDMIC->PDMIC_MR = (1u << 4) | PDMIC_MR_PRESCAL(1);

/* Set oversampling ratio to 64 */
PDMIC->PDMIC_DSPR0 = PDMIC_DSPR0_OSR(1);

/* Set DGAIN to 1 */
PDMIC->PDMIC_DSPR1 = PDMIC_DSPR1_DGAIN(1);

/* Enable PDMIC */
PDMIC->PDMIC_CR = PDMIC_CR_ENPDM;

/* Enable DMA channel */
XDMAC0->XDMAC_GE = XDMAC_GE_EN0;

/* Wait until DMA transfer is done */
while(!(XDMAC0->XDMAC_CHID[0].XDMAC_CIS & XDMAC_CIS_BIS));

The Audio PLL clock output of 98.304 MHz is fed to the PDMIC module after prescaling it down to 12.288 MHz using the GCLK controller in PMC (GCKDIV is set to 7, so the GCLK division factor is 8).

The PDMIC module is configured with an oversampling ratio of 64 with unity gain and then enabled. Once enabled, the PDMIC generates the PDM clock and then starts to convert audio data.

The XDMAC channel is also enabled, which starts transferring the converted result from PDMIC to the buffer in the main memory. The XDMAC channel block interrupt flag (BIS) is set once the specified number of micro block length data are transferred to the main memory, and the CPU comes out of the last while loop in the above code snippet.

The overall gain of the PDMIC module can be configured by modifying the DGAIN and SCALE parameters, which follow the equation below (assuming offset and shift are zero).