4.5 CLASSD PWM Stage

The CLASSD Pulse Width Modulator (PWM) generates fixed-frequency PWM outputs. The following table shows the PWM frequency generated for different sample rates and conditions.

Depending on the NON_OVERLAP bit value in the mode register (CLASSD_MR), the CLASSD can:

• Work as a DAC, loaded by a medium-to-high resistive load (1 kΩ to 100 kΩ) – Single-ended or differential resistive loads (NON_OVERLAP = 0), or
• Work as a CLASS D power amplifier driving an external power stage – Full or Half MOSFET H-bridges (NON_OVERLAP = 1)

When driving an external power stage (NON_OVERLAP = 1), the CLASSD generates the signals to control complementary MOSFET pairs (PMOS and NMOS) with a non-overlapping delay between the NMOS and PMOS controls to avoid short-circuit current. The non-overlapping delay can be adjusted in the CLASSD_MR.NOVRVAL field.

For each NON_OVERLAP bit value, the PWM stage can generate a single-ended or differential output depending on the PWMTYP bit available in the mode register.

For a single-ended output (CLASSD_MR.PWMTYP = 0), the PWM acts only on the falling edge of the PWM waveform (trailing edge PWM). For a differential output (CLASSD_MR.PWMTYP = 1), both the rising and the falling edges of the PWM waveform are modulated (symmetric PWM).

The following figures show the modulated PWM output waveforms when PWMTYP = 0 and when PWMTYP = 1, respectively.

To summarize the CLASSD outputs for the left channel:

1. When NON_OVERLAP = 0, in Single-ended mode (PWMTYP = 0), only one PWM output signal is generated per channel (L0 for the left channel), and it covers both the positive and negative sides of the analog output.
2. When NON_OVERLAP = 0, in Differential mode (PWMTYP = 1), two PWM outputs are generated per channel (L0 and L2 for the left channel), where one PWM output covers the positive half and another PWM output covers the negative half of the analog output.
3. When NON_OVERLAP = 1, in Single-ended mode (PWMTYP = 0), two PWM outputs are generated per channel (L0 and L1 for the left channel) to drive a single PMOS-NMOS complementary pair. These two PWM outputs are exactly the same, with a small delay between them during the level transition (edges) to avoid a short circuit. The output from the PMOS-NMOS complementary pair is now a single PWM signal covering both the positive and negative sides of the analog output.
4. When NON_OVERLAP = 1, in Differential mode (PWMTYP = 1), four PWM outputs are generated per channel (L0, L1, L2 and L3) to drive two PMOS-NMOS complementary pairs. The first two PWM outputs (L0 and L1) are used to drive the upper PMOS-NMOS complementary pair, and the next two PWM outputs (L2 and L3) are used to drive the lower PMOS-NMOS complementary pair. The effective PWM signal from the upper complementary pair covers the positive side of the analog output, and the effective PWM signal from the lower complementary pair covers the negative side of the analog output. An individual delay is applied to the PWM inputs of each complementary pair, just like in case 3 above, to avoid a short circuit.