1.2 I/O Glitch

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A glitch might occur during power-up or power-down for GPIO or HSIO outputs in PolarFire SoC devices. Glitch can occur before or after the device reaches a functional state. These glitches are not observed on LVDS outputs or Transceiver I/Os. No reliability issues are caused by either of the glitch types. Following are the types of glitches that can occur.

Parasitic glitches might occur for GPIOs or HSIOs before the device reaches functional state with a maximum glitch of 1V with a 0.4 ms width. This type of glitch can typically be ignored. It is recommended to use a 100K pull-down resistor on critical signals^¹ of the GPIO or HSIO pins if this type of glitch cannot be ignored. No glitches are observed once mitigation recommendations are placed. This may occur for both erased/blank and programmed units.
Another type of glitch might occur on GPIOs and HSIOs during power-on sequencing or boot-up. This is due to a weak pull-up resistor being enabled by default on an input, output or bidirectional I/O. To mitigate this glitch, use the Libero SoC I/O Editor or PDC constraint to program a weak pull-down on the output buffer on the specified I/O. This might occur for both erased/blank and programmed units.
The last type of glitch might occur after the device reaches functional state and might occur for both erased/blank and programmed units. This type of glitch is related to the power-up and power-down sequence of VDDI and VDDAUX supplies. This occurs only on GPIOs where the VDDI is 1.5V or 1.8V only with a maximum glitch of 1V with a 0.8 ms width during power-up and a maximum glitch of 1.8V with a 1 ms width during power down. For HSIOs where the VDDI is 1.5V or 1.8V only a maximum glitch of 600 mV and 1.5 ms width might occur at power-up and a maximum glitch of 220 mV and 200 µs width might occur at power-down.

To mitigate the post functional state glitch, follow the recommendations in the following tables.

Table 1-9. Power Sequencing¹ (For GPIO)
Use Cases for GPIO		Power-up Sequencing Requirement for Mitigating Glitches²	Power-down Sequencing Requirements for Mitigating Glitches²
VDDI	VDDAUX	—	—
1.2V	2.5V	No glitch occurs	No glitch occurs
1.5V	2.5V	Power up VDDAUX before VDDI of that bank	Power down VDDI before VDDAUX of that bank
1.8V	2.5V	Power up VDDAUX before VDDI of that bank	Power down VDDI before VDDAUX of that bank
2.5V	2.5V	Power VDDAUX and VDDI from the same regulator	No glitch occurs
3.3V	3.3V	Power VDDAUX and VDDI from the same regulator	No glitch occurs
⁽¹⁾ No glitches are observed once mitigation recommendations are placed. ⁽²⁾ This power sequence does not mitigate any parasitic glitches. As mentioned, add a 100K pull-down resistor to critical signals of GPIO or HSIO pins for mitigation of parasitic glitches.

Table 1-10. Power Sequencing¹ (For HSIO)
Use Cases for HSIO		Power-up Sequencing Requirement for Mitigating Glitches²	Power-down Sequencing Requirements for Mitigating Glitches²
VDDI	VDD18	—	—
1.2V	1.8V	No glitch occurs	No glitch occurs
1.5V	1.8V	Power up VDD18 before VDDI of that bank	Power down VDDI before VDD18, VDD, VDD25 of that bank
1.8V	1.8V	Power up VDD18 before VDDI of that bank	Power down VDDI before VDD18, VDD, VDD25 of that bank
⁽¹⁾ No glitches are observed once mitigation recommendations are placed. ⁽²⁾ This power sequence does not mitigate any parasitic glitches. As mentioned, add a 100K pull-down resistor to critical signals of GPIO or HSIO pins for mitigation of parasitic glitches.

Important: A glitch can occur on GPIO pins during JTAG programming if power is disrupted. The glitch can be mitigated by powering down VDDI before VDDAUX, VDD, and VDDI3.

Critical outputs such as reset or clock of the HSIO or GPIOs going into another device.