1.3 User I/O

PolarFire SoC FPGAs have two types of I/O buffers: HSIO and GPIO. HSIO buffers are optimized for 
single-ended buffers with supplies from 1.2V to 1.8V. GPIO buffers support single-ended and true differential interfaces with supplies from 1.2V to 3.3V. PolarFire SoC FPGAs support the following types of I/O Banks:

  • GPIO Banks—These Banks support I/O buffers for single-ended and true differential signals from 1.2V to 3.3V.
  • HSIO Banks—These Banks support optimized I/O buffers for single-ended and true differential signals from 1.2V to 1.8V.
  • MSS I/Os—These banks can support I/O buffer for single-ended signals from 1.2V to 3.3V.
  • MSS DDR I/Os—These banks can support I/O buffer for single-ended and differential per the Pin table signals at 1.2V, 1.5V to 1.8V.
  • MSS SGMII I/Os—These banks can support I/O buffer for single-ended and differential per the Pin table signals at 2.5V or 3.3V.
Note: When the HSIO bank is configured as an LVDS receiver, the concerned I/Os must be connected externally by a 100Ω resistor.

For more information about key features of I/O buffers and supported standards, see PolarFire SoC FPGA Packaging and Pin Descriptions User Guide and PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide.