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PolarFire SoC FPGA Board Design Guidelines
PolarFire SoC FPGA Board Design Guidelines
  1. Home
  2. 1 Designing the Board
  3. 1.4 MSS I/Os

  • Introduction
  • 1 Designing the Board
    • 1.1 Power Supplies
    • 1.2 I/O Glitch
    • 1.3 User I/O
    • 1.4 MSS I/Os
      • 1.4.1 MSS DDR I/Os
      • 1.4.2 MSS SGMII I/Os
      • 1.4.3 MSS-Specific I/O
    • 1.5 Clocks
    • 1.6 Reset
    • 1.7 DDR
    • 1.8 Device Programming
    • 1.9 Special Pins
    • 1.10 Transceiver
    • 1.11 MIPI Hardware Design Guidelines
    • 1.12 AC and DC Coupling
    • 1.13 Brownout Detection
  • 2 Board Design Checklist
  • 3 Appendix: General Layout Design Practices
  • 4 Revision History
  • Microchip FPGA Support
  • Microchip Information

1.4 MSS I/Os

(Ask a Question)

PolarFire SoC FPGAs support the following type of MSS I/O buffers.

  • MSS DDR I/Os
  • MSS SGMII I/Os
  • MSS-Specific I/O

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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