13.14.10.5 Next Descriptor Address

The DESCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10

Name:	DESCADDR
Offset:	0x0C
Reset:	-
Property:	-


Bit	31	30	29	28	27	26	25	24
	DESCADDR[31:24]
Access	-	-	-	-	-	-	-	-
Reset


Bit	23	22	21	20	19	18	17	16
	DESCADDR[23:16]
Access	-	-	-	-	-	-	-	-
Reset


Bit	15	14	13	12	11	10	9	8
	DESCADDR[15:8]
Access	-	-	-	-	-	-	-	-
Reset


Bit	7	6	5	4	3	2	1	0
	DESCADDR[7:0]
Access	-	-	-	-	-	-	-	-
Reset

Bits 31:0 – DESCADDR[31:0] Next Descriptor Address

This bit group holds the LP SRAM address of the next descriptor. The value must be 128-bit aligned. If the value of this LP SRAM register is 0x00000000, the transaction will be terminated when the DMAC tries to load the next transfer descriptor.