13.14.10.1 Block Transfer Control

These bits select the address increment step size. The setting apply to source or destination address, depending on STEPSEL setting.

This bit selects if source or destination addresses are using the step size settings.

Writing a '0' to this bit will disable the destination address incrementation. The address will be kept fixed during the data transfer.

Writing a '1' to this bit will enable the destination address incrementation. By default, the destination address is incremented by 1. If the STEPSEL bit is cleared, flexible step-size settings are available in the STEPSIZE register.

Writing a '0' to this bit will disable the source address incrementation. The address will be kept fixed during the data transfer.

Writing a '1' to this bit will enable the source address incrementation. By default, the source address is incremented by 1. If the STEPSEL bit is set, flexible step-size settings are available in the STEPSIZE register.

These bits define the size of one beat. A beat is the size of one data transfer bus access, and the setting apply to both read and write accesses.

These bits define what actions the DMAC should take after a block transfer has completed.

These bits define the event output selection.

Writing a '0' to this bit in the Descriptor or Write-Back memory will suspend the DMA channel operation when fetching the corresponding descriptor.

The bit is automatically cleared in the Write-Back memory section when channel is aborted, when an error is detected during the block transfer, or when the block transfer is completed.