13.30.7.1 Front-End Control

Name: FECTRL
Offset: 0x00
Reset: 0x0000
Property: —

Bit 15141312111098 
     F5CFG[1:0]F4CFG[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 F3CFG[1:0]F2CFG[1:0]F1CFG[1:0]F0CFG[1:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 11:10 – F5CFG[1:0]

These bits define the front-end output control signal 5, as shown in Table 13-99.

Bits 9:8 – F4CFG[1:0]

These bits define the front-end output control signal 4, as shown in Table 13-99.

Bits 7:6 – F3CFG[1:0]

These bits define the front-end output control signal 3, as shown in Table 13-99.

Bits 5:4 – F2CFG[1:0]

These bits define the front-end output control signal 2, as shown in Table 13-99.

Bits 3:2 – F1CFG[1:0]

These bits define the front-end output control signal 1, as shown in Table 13-99.

Bits 1:0 – F0CFG[1:0]

These bits define the front-end output control signal 0, as shown in Table 13-99.
Table 13-99. Front-End Control Configuration
FnCFG[1:0] Operating Mode
0x0 Route transceiver DIG1 signal output to FECTRL[n] alternate pin function.
0x1 Route transceiver DIG2 signal output to FECTRL[n] alternate pin function.
0x2 Route transceiver DIG3 signal output to FECTRL[n] alternate pin function.
0x3 Route transceiver DIG4 signal output to FECTRL[n] alternate pin function.