13.17.8.12 Event Input Control

The I/O pins are assembled in PORT groups with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each PORT group has its own set of PORT registers with offset 0x80. The available number of PORT groups may depend on the package/pin number of the device.

There are up to four input event pins for each PORT group. Each byte of this register addresses one Event input pin.
Name: EVCTRL
Offset: 0x2C
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
 PORTEIxEVACTx[1:0]PIDx[4:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 PORTEIxEVACTx[1:0]PIDx[4:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 PORTEIxEVACTx[1:0]PIDx[4:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 PORTEIxEVACTx[1:0]PIDx[4:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 31,23,15,7 – PORTEIx PORT Event Input Enable x [x = 3..0]

ValueDescription
0 The event action x (EVACTx) will not be triggered on any incoming event.
1 The event action x (EVACTx) will be triggered on any incoming event.

Bits 30:29, 22:21,14:13,6:5 – EVACTx PORT Event Action x [x = 3..0]

These bits define the event action the PORT will perform on event input x. See also Table 13-49.

Bits 28:24,20:16,12:8,4:0 – PIDx PORT Event Pin Identifier x [x = 3..0]

These bits define the I/O pin on which the event action will be performed, according to Table 13-50.

Table 13-49. PORT Event x Action ( x = [3..0] )
Value Name Description
0x0 OUT Output register of pin will be set to level of event.
0x1 SET Set output register of pin on event.
0x2 CLR Clear output register of pin on event.
0x3 TGL Toggle output register of pin on event.
Table 13-50. PORT Event x Pin Identifier ( x = [3..0] )
Value Name Description
0x0 PIN0 Event action to be executed on PIN 0.
0x1 PIN1 Event action to be executed on PIN 1.
... ... ...
0x31 PIN31 Event action to be executed on PIN 31.