13.8.6.3.7 Regulators, RAMs and NVM State in Sleep Mode

By default, in Standby Sleep mode and backup sleep mode, the RAMs, NVM and regulators are automatically set in Low-Power mode to reduce power consumption:

  • The RAM is in Low-Power mode if its power domain is in retention or off state. Refer to RAM Automatic Low Power Mode for details.
  • Non-Volatile Memory – The NVM is located in the power domain PD2 . By default, the NVM is automatically set in low power mode in these conditions:
    • When the power domain PD2 is in a retention or off state.
    • When the device is in Standby Sleep mode and the NVM is not accessed. This behavior can be changed by software by configuring the SLEEPPRM bit group of the CTRLB register in the NVMCTRL peripheral.
    • When the device is in Idle Sleep mode and the NVM is not accessed. This behavior can be changed by software by configuring the SLEEPPRM bit group of the CTRLB register in the NVMCTRL peripheral.
  • Regulators: By default, in Standby Sleep mode, the PM analyzes the device activity to use either the main or the low-power voltage regulator to supply the VDDCORE.

GCLK clocks, regulators and RAM are not affected in the Idle Sleep mode and will operate as normal.

Table 13-24. Regulators, RAMs and NVM state in Sleep Mode
Sleep

Mode

 Switchable Power Domains RAMs mode(1) NVM Regulators
PD0 PD1 PD2 LP SRAM SRAM VDDCORE VDDBU
main ulp
Active active active active normal normal normal on on on
Idle active active active normal auto(2) on on on on
Standby – Case 2 active active retention normal low power low power auto(3) on on
Standby – Case 3 active retention retention low power low power low power auto(3) on on
Standby – Case 4 retention retention retention low power low power low power off on on
Backup off off off off off off off off on
Note:
  1. RAMs mode by default: STDBYCFG.BBIAS bits are set to their default value.
  2. Auto: By default, NVM is in low-power mode, if not accessed.
  3. Auto: By default, the main voltage regulator is on if GCLK, APBx or AHBx clock is running during SleepWalking.
  4. For a description of the cases, see 13.8.6.3.6 Power Domain Controller.