13.22.6.6 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read.

The following bits are synchronized when written:

Software Reset bit in the CTRLA register (CTRLA.SWRST)
Enable bit in the CTRLA register (CTRLA.ENABLE)
Write to Bus State bits in the Status register (STATUS.BUSSTATE)
Address bits in the Address register (ADDR.ADDR) when in master operation.

The following registers are synchronized when written:

Data (DATA) when in master operation

Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.

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