13.8.6.6.2 Dynamic SleepWalking Based on Event

To enable SleepWalking with dynamic power domain gating, the Dynamic Power Gating for Power Domain 0 and 1 bits in the Standby Configuration register (STDBYCFG.DPGPD0 and STDBYCFG.DPGPD1) have to be written to '1'.

When in retention state, a power domain can be automatically set to an active state by the PM if an event is directed to this power domain. In this device, this concerns the event users located in power domains PD1 and PD0 .

  • When PD0, PD1 and PD2 are in retention state, dynamic SleepWalking can be triggered by an:
    • AC output event
    • RTC output event
    • EIC output event (if using the CLK_ULP32K clock)
  • When PD0 is active, and while PD1 and PD2 are in retention state, dynamic SleepWalking can be triggered by an:
    • RTC output event
    • EIC output event (if using CLK_ULP32K)
    • All peripheral within PD0 that are capable of generating events

    All modules located in PD0 can generate events. The EVSYS event generator must be configured to either a synchronous or resynchronized path.

  • When PD0 and PD1 are in retention, dynamic SleepWalking based on event is not useful.

Also refer to 13.8.6.1.2 Power Domains.

Dynamic SleepWalking based on event is illustrated in the following example:

Figure 13-29. Dynamic SleepWalking Based on Event: AC Periodic Comparison

The Analog Comparator (AC) peripheral is used in Single Shot mode to monitor voltage levels on input pins. A comparator interrupt, based on the AC peripheral configuration, is generated to wake up the device. In the GCLK module, the AC generic clock (GCLK_AC) source is routed to a 32.768 kHz oscillator (for low power applications, OSC32KULP is recommended). RTC and EVSYS modules are configured to generate periodic events to the AC. To make the comparator continue to run in standby sleep mode, the RUNSTDBY bit is written to '1'. To enable the dynamic SleepWalking for the PD0 power domain, STDBYCFG.DPGPD0 must be written to '1'.

Entering standby mode: The Power Manager sets the PD0 power domain (where the AC module is located) in retention state, as well as PD1 and PD2. The AC comparators, COMPx, are OFF. The GCLK_AC clock is stopped. The VDDCORE is supplied by the low power regulator.

Dynamic SleepWalking: The RTC event (RTC_PERX) is routed by the Event System to the Analog Comparator to trigger a single-shot measurement. This event is detected by the Power Manager, which sets the PD0 power domain to an active state, and starts the main voltage regulator.

After enabling the AC comparator and starting the GCLK_AC, the single-shot measurement can be performed during sleep mode (sleepwalking task); refer to 13.28.6.14.2 Single-Shot Measurement during Sleep for details. At the end of the conversion, if conditions to generate an interrupt are not met, the GCLK_AC clock and the AC comparator are stopped again.

The low power regulator starts again, and the PD0 power domain is set back to a retention state by the PM. Note that during this dynamic SleepWalking period, the CPU is still sleeping.

Exiting standby mode: During the dynamic SleepWalking sequence, if conditions are met, the AC module generates an interrupt to wake up the device. Successively, the PD1 and PD2 power domain are set to an active state by the PM.