11.4.2 Configuration
High-Speed Bus Matrix Masters | Master ID |
---|---|
CM0+ - Cortex M0+ Processor | 0 |
DSU - Device Service Unit | 1 |
L2HBRIDGEM - Low-Power to High-Speed bus matrix AHB to AHB bridge | 2 |
High-Speed Bus Matrix Slaves | Slave ID |
---|---|
Internal Flash Memory | 0 |
HS SRAM Port 0 - CM0+ Access | 1 |
HS SRAM Port 1 - DSU Access | 2 |
AHB-APB Bridge B | 3 |
H2LBRIDGES - High-Speed to Low-Power bus matrix AHB to AHB bridge | 4 |
Low-Power Bus Matrix Masters | Master ID |
---|---|
H2LBRIDGEM - High-Speed to Low-Power bus matrix AHB to AHB bridge | 0 |
DMAC - Direct Memory Access Controller - Data Access | 2 |
Low-Power Bus Matrix Slaves | Slave ID |
---|---|
AHB-APB Bridge A | 0 |
AHB-APB Bridge C | 1 |
AHB-APB Bridge D | 2 |
AHB-APB Bridge E | 3 |
LP SRAM Port 2- H2LBRIDGEM access | 5 |
LP SRAM Port 1- DMAC access | 7 |
L2HBRIDGES - Low-Power to High-Speed bus matrix AHB to AHB bridge | 8 |
HS SRAM Port 2- HMATRIXLP access | 9 |