11.4.2 Configuration

Figure 11-2. Master-Slave Relations High-Speed Bus Matrix
Figure 11-3. Master-Slave Relations Low-Power Bus Matrix
Table 11-4. High-Speed Bus Matrix Masters
High-Speed Bus Matrix Masters Master ID
CM0+ - Cortex M0+ Processor 0
DSU - Device Service Unit 1
L2HBRIDGEM - Low-Power to High-Speed bus matrix AHB to AHB bridge 2
Table 11-5. High-Speed Bus Matrix Slaves
High-Speed Bus Matrix Slaves Slave ID
Internal Flash Memory 0
HS SRAM Port 0 - CM0+ Access 1
HS SRAM Port 1 - DSU Access 2
AHB-APB Bridge B 3
H2LBRIDGES - High-Speed to Low-Power bus matrix AHB to AHB bridge 4
Table 11-6. Low-Power Bus Matrix Masters
Low-Power Bus Matrix Masters Master ID
H2LBRIDGEM - High-Speed to Low-Power bus matrix AHB to AHB bridge 0
DMAC - Direct Memory Access Controller - Data Access 2
Table 11-7. Low-Power Bus Matrix Slaves
Low-Power Bus Matrix Slaves Slave ID
AHB-APB Bridge A 0
AHB-APB Bridge C 1
AHB-APB Bridge D 2
AHB-APB Bridge E 3
LP SRAM Port 2- H2LBRIDGEM access 5
LP SRAM Port 1- DMAC access 7
L2HBRIDGES - Low-Power to High-Speed bus matrix AHB to AHB bridge 8
HS SRAM Port 2- HMATRIXLP access 9