11.4.1 Features

High-Speed Bus Matrix has the following features:

  • Symmetric crossbar bus switch implementation
  • Allows concurrent accesses from different masters to different slaves
  • 32-bit data bus
  • Operation at a one-to-one clock frequency with the bus masters
H2LBRIDGE has the following features:
  • LP clock division support
  • Write: Posted-write FIFO of 3 words, no bus stall until it is full
  • Write: 1 cycle bus stall when full when LP clock is not divided
  • 2 stall cycles on read when LP clock is not divided
  • Ultra low latency mode:
    • Suitable when the HS clock frequency is not above half the maximum device clock frequency
    • Removes all intrinsic bridge stall cycles (except those needed for LP clock ratio adaptation)
    • Enabled by writing a '1' in 0x41008120 using a 32-bit write access
L2HBRIDGE has the following features:
  • LP clock division support
  • Write: Posted-write FIFO of 1 word, no bus stall until it is full
  • Write: 1 cycle bus stall when full when LP clock is not divided
  • 2 stall cycles on read when LP clock is not divided
  • ultra low latency mode:
    • Suitable when the HS clock frequency is not above half the maximum device clock frequency
    • Removes all intrinsic bridge stall cycles (except those needed for LP clock ratio adaptation)
    • Enabled by writing a '1' in 0x41008120 using a 32-bit write access
Figure 11-1. High-Speed Bus System Components