11.4.3 SRAM Quality of Service

To ensure that masters with latency requirements get sufficient priority when accessing RAM, priority levels can be assigned to the masters for different types of access.

The Quality of Service (QoS) level is independently selected for each master accessing the RAM. For any access to the RAM, the RAM also receives the QoS level. The QoS levels and their corresponding bit values for the QoS level configuration are shown in the following table.

Table 11-8. Quality of Service
Value Name Description
0x0 DISABLE Background (no sensitive operation)
0x1 LOW Sensitive Bandwidth
0x2 MEDIUM Sensitive Latency
0x3 HIGH Critical Latency

If a master is configured with QoS level DISABLE (0x0) or LOW (0x1) there will be a minimum latency of one cycle for the RAM access.

The priority order for concurrent accesses are decided by two factors. First, the QoS level for the master and second, a static priority given by the port ID. The lowest port ID has the highest static priority. See the tables below for details.

The MTB has a fixed QoS level HIGH (0x3).

The CPU QoS level can be written/read, using 32-bit access only, at address 0x41008114 bits [1:0]. Its reset value is 0x3.

Refer to different master QOSCTRL registers for configuring QoS for the other masters (USB, DMAC).

Table 11-9. HS SRAM Port Connections QoS
HS SRAM Port Connection Port ID Connection Type QoS default QoS
MTB - Micro Trace Buffer 4 Direct STATIC-3 0x3
USB - Universal Serial Bus 3 Direct IP-QOSCTRL 0x3
HMATRIXLP - Low-Power Bus Matrix 2 Bus Matrix 0x44000934(1), bits[1:0] 0x2
DSU - Device Service Unit 1 Bus Matrix 0x4100201C(1) 0x2
CM0+ - Cortex M0+ Processor 0 Bus Matrix 0x41008114(1), bits[1:0] 0x3
Note:
  1. Using 32-bit access only.
Table 11-10. LP SRAM Port Connections QoS
LP SRAM Port Connection Port ID Connection Type QoS default QoS
DMAC - Direct Memory Access Controller - Write-Back Access 5, 6 Direct IP-QOSCTRL.WRBQOS 0x2
DMAC - Direct Memory Access Controller - Fetch Access 3, 4 Direct IP-QOSCTRL.FQOS 0x2
H2LBRIDGEM - HS to LP bus matrix AHB to AHB bridge 2 Bus Matrix 0x44000924(1), bits[1:0] 0x2
DMAC - Direct Memory Access Controller - Data Access 1 Bus Matrix IP-QOSCTRL.DQOS 0x2
Note:
  1. Using 32-bit access only.