13.4.7 Clocks after Reset
On any Reset, the synchronous clocks start to their initial state:
- OSC16M is enabled and configured to run at 4 MHz
- Generic Generator 0 uses OSC16M as source and generates GCLK_MAIN
- CPU and BUS clocks are undivided
On a Power Reset, the 32 KHz clock sources are reset, and the GCLK module starts to its initial state:
- All Generic Clock
Generators are disabled except
- Generator 0 is using OSC16M at 4 MHz as source and generates GCLK_MAIN
- All Peripheral Channels in GCLK are disabled
On a User Reset, the GCLK module starts in its initial state, except for:
- Generic Clocks that are write-locked, i.e., the according WRTLOCK is set to 1 prior to Reset