13.27.6.2.4 Prescaler Selection

The ADC is clocked by GCLK_ADC. There is also a prescaler in the ADC to enable conversion at lower clock rates. Refer to CTRLB for details on prescaler settings. Refer to 13.27.6.2.8 Conversion Timing and Sampling Rate for details on timing and sampling rate.

Figure 13-204. ADC Prescaler

Note: The minimum prescaling factor is DIV2.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.