10.2 Physical Memory Map

The high-speed bus is implemented as a bus matrix. All high-speed bus addresses are fixed, and they are never remapped in any way, even during boot. The 32-bit physical address space is mapped as follows:

Table 10-1. SAM R30 Physical Memory Map⁽¹⁾
Memory	Start address	Size [KB]
Memory	Start address	SAMR30x18
Embedded Flash	0x00000000	256
Embedded RWW section	0x00400000	8
Embedded SRAM	0x20000000	32
Embedded low-power SRAM	0x30000000	8
Peripheral Bridge A	0x40000000	64
Peripheral Bridge B	0x41000000	64
Peripheral Bridge C	0x42000000	64
Peripheral Bridge D	0x43000000	64
Peripheral Bridge E	0x44000000	64
IOBUS	0x60000000	0.5

1. x = G or E.

Table 10-2. Flash Memory Parameters⁽¹⁾
Device	Flash size [KB]	Number of pages	Page size [Bytes]
SAMR30x18	256	4096	64

1. x = G or E.

Table 10-3. RWW Section Parameters⁽¹⁾
Device	Flash size [KB]	Number of pages	Page size [Bytes]
SAMR30x18	8	128	64

1. x = G or E.