26.7.2 Control B


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
							READMODE[1:0]
Access							R/W	R/W
Reset							0	0


Bit	15	14	13	12	11	10	9	8
							SLEEPPRM[1:0]
Access							R/W	R/W
Reset							0	0


Bit	7	6	5	4	3	2	1	0
				RWS[3:0]
Access				R/W	R/W	R/W	R/W
Reset				0	0	0	0

Bits 17:16 – READMODE[1:0] NVMCTRL Read Mode

Value	Name	Description
0x0	NO_MISS_PENALTY	The NVM Controller (cache system) does not insert Wait states on a cache miss. Gives the best system performance.
0x1	LOW_POWER	Reduces power consumption of the cache system, but inserts a Wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increased run time.
0x2	DETERMINISTIC	The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed Flash Wait states. This mode can be used for real-time applications that require deterministic execution timings.
0x3	Reserved

Bits 9:8 – SLEEPPRM[1:0] Power Reduction mode during Sleep

Indicates the Power Reduction mode during sleep.

Value	Name	Description
0x0	WAKEUPACCESS	NVM block enters Low-Power mode when entering sleep.  NVM block exits Low-Power mode upon first access.
0x1	WAKEUPINSTANT	NVM block enters Low-Power mode when entering sleep.  NVM block exits Low-Power mode when exiting sleep.
0x2	Reserved
0x3	DISABLED	Auto power reduction disabled.

Bits 4:1 – RWS[3:0] NVM Read Wait States

These bits control the number of Wait states for a read operation. '0' indicates zero Wait states, '1' indicates one wait state, etc., up to 15 wait states.

This register is initialized to 0 wait states. Software can change this value based on the NVM access time and system frequency.

Name:	CTRLB
Offset:	0x04
Reset:	0x00000080
Property:	PAC Write-Protection