36.7.1 Control A

Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized Bits

Bit 76543210 
 ONDEMANDRUNSTDBY    ENABLESWRST 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 7 – ONDEMAND On Demand Control

The On-Demand operation mode allows the ADC to be enabled or disabled, depending on other peripheral requests.

In On-Demand operation mode, i.e., if the ONDEMAND bit has been previously set, the ADC will only be running when requested by a peripheral. If there is no peripheral requesting the ADC will be in a disabled state.

If O- Demand is disabled the ADC will always be running when enabled.

In Standby Sleep mode, the On-Demand operation is still active if the CTRLA.RUNSTDBY bit is '1'. If the CTRLA.RUNSTDBY bit is '0', the ADC is disabled.

Note: This bit is not synchronized.

For the client ADC, this bit has no effect when the SLAVEEN bit is set (CTRLA.SLAVEEN = 1). The ONDEMAND bit from host ADC instance will control the On-Demand operation mode.

ValueDescription
0 The ADC is always on , if enabled.
1 The ADC is enabled, when a peripheral is requesting the ADC conversion. The ADC is disabled if no peripheral is requesting it.

Bit 6 – RUNSTDBY Run in Standby

This bit controls how the ADC behaves during Standby Sleep mode.

Note: This bit is not synchronized.
ValueDescription
0 The ADC is halted during Standby Sleep mode.
1 The ADC is not stopped in Standby Sleep mode. If CTRLA.ONDEMAND = 1, the ADC will be running when a peripheral is requesting it. If CTRLA.ONDEMAND = 0, the ADC will always be running in Standby Sleep mode.

Bit 1 – ENABLE Enable

Note: This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE.

For the client ADC, this bit has no effect when the SLAVEEN bit is set (CTRLA.SLAVEEN = 1).

ValueDescription
0 The ADC is disabled.
1 The ADC is enabled.

Bit 0 – SWRST Software Reset

Writing a '0' to this bit has no effect.

Writing a '1' to this bit resets all registers in the ADC, except DBGCTRL, to their initial state, and the ADC will be disabled.

Writing a '1' to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.

Note: This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the CTRLA.SWRST synchronization is complete.
ValueDescription
0 There is no reset operation ongoing.
1 The reset operation is ongoing.