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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
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Product Pages
SAM9X60
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46
Flexible Serial Communication Controller (FLEXCOM)
46.7
USART Functional Description
46.7.8
LIN Mode
46.7.8.5
Character Reception
Introduction
Features
Reference Document
1
Configuration Summary
2
Block Diagram
3
Signal Description
4
Microchip Recommended Power Management Solutions
5
Safety and Security Features
6
Package and Pinout
7
Memories
8
System Controller
9
Peripherals
10
ARM926EJ-S Processor
11
Debug and Test
12
Boot Strategies
13
System Controller Write Protection (SYSCWP)
14
General Purpose Backup Registers (GPBR)
15
Watchdog Timer (WDT)
16
Reset Controller (RSTC)
17
Real-Time Timer (RTT)
18
Real-Time Clock (RTC)
19
Shutdown Controller (SHDWC)
20
Periodic Interval Timer (PIT)
21
64-bit Periodic Interval Timer (PIT64B)
22
Debug Unit (DBGU)
23
OTP Memory Controller (OTPC)
24
Special Function Registers (SFR)
25
Bus Matrix (MATRIX)
26
Advanced Interrupt Controller (AIC)
27
Slow Clock Controller (SCKC)
28
Clock Generator
29
Power Management Controller (PMC)
30
Parallel Input/Output Controller (PIO)
31
External Bus Interface (EBI)
32
DDR-SDRAM Controller (MPDDRC)
33
SDRAM Controller (SDRAMC)
34
Static Memory Controller (SMC)
35
Programmable Multibit Error Correction Code Controller (PMECC)
36
Programmable Multibit ECC Error Location Controller (PMERRLOC)
37
DMA Controller (XDMAC)
38
LCD Controller (LCDC)
39
2D Graphics Engine (GFX2D)
40
Ethernet MAC 10/100 (EMAC)
41
USB Device High Speed Port (UDPHS)
42
USB Host High Speed Port (UHPHS)
43
Audio Class D Amplifier (CLASSD)
44
Inter-IC Sound Multi-Channel Controller (I2SMCC)
45
Synchronous Serial Controller (SSC)
46
Flexible Serial Communication Controller (FLEXCOM)
46.1
Description
46.2
Embedded Characteristics
46.3
Block Diagram
46.4
I/O Lines Description
46.5
Product Dependencies
46.6
Register Accesses
46.7
USART Functional Description
46.7.1
Baud Rate Generator
46.7.2
Receiver and Transmitter Control
46.7.3
Synchronous and Asynchronous Modes
46.7.4
ISO7816 Mode
46.7.5
IrDA Mode
46.7.6
RS485 Mode
46.7.7
USART Comparison Function on Received Character
46.7.8
LIN Mode
46.7.8.1
Modes of Operation
46.7.8.2
Baud Rate Configuration
46.7.8.3
Receiver and Transmitter Control
46.7.8.4
Character Transmission
46.7.8.5
Character Reception
46.7.8.6
Header Transmission (Host Node Configuration)
46.7.8.7
Header Reception (Client Node Configuration)
46.7.8.8
Client Node Synchronization
46.7.8.9
Identifier Parity
46.7.8.10
Node Action
46.7.8.11
Response Data Length
46.7.8.12
Checksum
46.7.8.13
Frame Slot Mode
46.7.8.14
LIN Errors
46.7.8.15
LIN Frame Handling
46.7.8.16
LIN Frame Handling with the
DMA
46.7.8.17
Wakeup Request
46.7.8.18
Bus Idle Timeout
46.7.9
LON Mode
46.7.10
Test Modes
46.7.11
USART FIFOs
46.7.12
16-bit Data Protocol Support
46.7.13
USART Register Write Protection
46.8
SPI Functional Description
46.9
TWI Functional Description
46.10
Register Summary
47
Quad Serial Peripheral Interface (QSPI)
48
Secure Digital MultiMedia Card Controller (SDMMC)
49
Image Sensor Interface (ISI)
50
Controller Area Network (CAN)
51
Timer Counter (TC)
52
Pulse Width Modulation Controller (PWM)
53
Advanced Encryption Standard (AES)
54
Secure Hash Algorithm (SHA)
55
Triple Data Encryption Standard (TDES)
56
Random Number Generator (TRNG)
57
Analog-to-Digital Controller (ADC)
58
Electrical Characteristics
59
Mechanical Characteristics
60
Marking
61
Ordering Information
62
Revision History
Microchip Information
46.7.8.5 Character Reception
See
Receiver Operations
.
