58.9.2.2 ULP1 Operation

Unlike the ULP0 mode, all the clocks are off in the ULP1 mode, and the number of wake-up sources is limited to the list below:
  • WKUP[13:1] pins (level transition, configurable debouncing)
  • RTC/RTT alarm
  • USB Resume from Suspend mode
  • Wake-On-LAN events from EMAC peripherals

The sequence to enter ULP1 mode is detailed below. The code used to enter this mode must be executed out of the internal SRAM0.

  1. Set the DDR to Self-refresh mode.
  2. Disable PMC_SCDR.DDRCLK.
  3. Set the events to enable a system wake-up.
  4. Disable all peripheral clocks.
  5. Set the I/Os to an appropriate state and disable the USB transceivers (refer to 24 Special Function Registers (SFR)).
  6. Switch the system clock to the 12 MHz RC oscillator.
  7. Set the SRAM memories to Light Sleep mode in SFR_LS.
  8. Disable the PLLs and the main oscillator.
  9. Enter ULP1 mode by setting the ULP1 bit in CKGR_MOR.

When resuming, the software reconfigures the system (oscillator, PLL, etc.) in the same state as before entering ULP1. In particular, the SRAM memories Light Sleep mode must be disabled as soon as possible in the wake-up process.