41.19 UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints) (Default Mode)

An OUT Short Packet is detected when the receive byte count is less than the configured UDPHS_EPTCFGx register EPT_Size.

This bit is updated at the same time as the BYTE_COUNT field.

It is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).

Byte count of a received data packet.

This field is incremented after each write into the endpoint (to prepare an IN transfer). It is decremented after each reading into the endpoint (OUT transfer).

This field is also updated at RXRDY_TXKL flag clear with the next bank, and at TXRDY flag set with the next bank.

This field is reset by UDPHS_EPTRST.EPT_x.

These bits are set by hardware to indicate the number of busy banks.

IN endpoint: Indicates the number of busy banks filled by the user, ready for IN transfer.

OUT endpoint: Indicates the number of busy banks filled by OUT transaction from the Host.

0: A Control Write is requested by the Host.

• Set by hardware to indicate the number of the current bank.
• Reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
• The current bank is updated each time the user:

  • Sets the TX Packet Ready bit to prepare the next IN transfer and to switch to the next bank.

  • Clears the received OUT data bit to access the next bank.

This bit is set by hardware when a NAK handshake has been sent in response to an OUT or PING request from the Host.

This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint).

This bit is set by hardware when a NAK handshake has been sent in response to an IN request from the Host.

This bit is cleared by software.

For Control, Bulk and Interrupt endpoints.

This bit is set by hardware after a STALL handshake has been sent as requested by the UDPHS_EPTSTAx register FRCESTALL bit.

This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).

For Control endpoint only.

This bit is set by hardware when a valid SETUP packet has been received from the host.

It is cleared by the device firmware after reading the SETUP data from the endpoint FIFO.

This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint).

This bit is cleared by hardware after the host has acknowledged the packet.

For Multi-bank endpoints, this bit may remain clear even after software is set if another bank is available to transmit.

Hardware clear of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register TXRDY bit.

This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint).

This bit is set by hardware after an IN packet has been accepted (ACK’ed) by the host.

This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint).

• This bit is set by hardware after a new packet has been stored in the endpoint FIFO.
• This bit is cleared by the device firmware after reading the OUT data from the endpoint.
• For multi-bank endpoints, this bit may remain active even when cleared by the device firmware, this if an other packet has been received meanwhile.
• Hardware assertion of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register RXRDY_TXKL bit.
• This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).

• The bank is really cleared or the bank is sent, BUSY_BANK_STA is decremented.
• The bank is not cleared but sent on the IN transfer, TX_COMPLT
• The bank is not cleared because it was empty. The user should wait that this bit is cleared before trying to clear another packet.
  Note: “Kill a packet” may be refused if at the same time, an IN token is coming and the current packet is sent on the UDPHS line. In this case, the TX_COMPLT bit is set. Take notice however, that if at least two banks are ready to be sent, there is no problem to kill a packet even if an IN token is coming. In fact, in that case, the current bank is sent (IN transfer) and the last bank is killed.

This bit is set by hardware when a new too-long packet is received.

Example: If the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an OUT transfer, then the Overflow Error bit is set.

This bit is updated at the same time as the BYTE_COUNT field.

This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).

In OUT transfer, the Toggle information is meaningful only when the current bank is busy (Received OUT Data = 1).

This field is updated for OUT transfer: 


• A new data has been written into the current bank.

• The user has just cleared the Received OUT Data bit to switch to the next bank.

This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx (disable endpoint).

Toggle Sequencing:

• IN endpoint: Indicates the PID Data Toggle that will be used for the next packet sent. This is not relative to the current bank.
• CONTROL and OUT endpoints: Set by hardware to indicate the PID data of the current bank.

This bit is reset by hardware upon received SETUP.