41.1 UDPHS Control Register
| Name: | UDPHS_CTRL |
| Offset: | 0x00 |
| Reset: | 0x00000200 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PULLD_DIS | REWAKEUP | DETACH | EN_UDPHS | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 1 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FADDR_EN | DEV_ADDR[6:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 11 – PULLD_DIS Pulldown Disable (cleared upon USB reset)
When set, there is no pulldown on DP & DM. (DM Pulldown = DP Pulldown = 0).
Note: If the DETACH bit is also set,
device DP & DM are left in High Impedance state.
See description of bit “DETACH”.
| DETACH | PULLD_DIS | DP | DM | Condition |
|---|---|---|---|---|
| 0 | 0 | Pullup | Pulldown | Not recommended |
| 0 | 1 | Pullup | High impedance state | VBUS present |
| 1 | 0 | Pulldown | Pulldown | No VBUS |
| 1 | 1 | High Impedance state | High Impedance state | VBUS present & software disconnect |
Bit 10 – REWAKEUP Send Remote Wake-Up (cleared upon USB reset)
An Upstream Resume is sent only after the UDPHS bus has been in Suspend state for at least 5 ms.
This bit is automatically cleared by hardware at the end of the Upstream Resume.
| Value | Description |
|---|---|
| 0 | Remote Wake-Up is disabled (read), or this bit has no effect (write). |
| 1 | Remote Wake-Up is enabled (read), or this bit forces an external interrupt on the UDPHS controller for Remote Wake-Up purposes. |
Bit 9 – DETACH Detach Command
See description of bit “PULL_DIS”.
| Value | Description |
|---|---|
| 0 | UDPHS is attached (read), or this bit pulls up the DP line (attach command) (write). |
| 1 | UDPHS is detached, UTMI transceiver is suspended (read), or this bit simulates a detach on the UDPHS line and forces the UTMI transceiver into Suspend state (Suspend M = 0) (write). |
Bit 8 – EN_UDPHS UDPHS Enable
| Value | Description |
|---|---|
| 0 | UDPHS is disabled (read), or this bit disables and resets the UDPHS controller (write). Switch the UHPHS to UTMI. |
| 1 | UDPHS is enabled (read), or this bit enables the UDPHS controller (write). Switch the UDPHS to UTMI. |
Bit 7 – FADDR_EN Function Address Enable (cleared upon USB reset)
| Value | Description |
|---|---|
| 0 | The device is not in Address state (read), or only the default function address is used (write). |
| 1 | The device is in Address state (read), or this bit is set by the device firmware after a successful status phase of a SET_ADDRESS transaction (write). When set, the only address accepted by the UDPHS controller is the one stored in the UDPHS Address field. It will not be cleared afterwards by the device firmware. It is cleared by hardware on hardware reset, or when UDPHS bus reset is received. |
Bits 6:0 – DEV_ADDR[6:0] UDPHS Address (cleared upon USB reset)
This field contains the default address (0) after power-up or UDPHS bus reset (read), or it is written with the value set by a SET_ADDRESS request received by the device firmware (write).