41.11 UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints) (Default Mode)

This register view is relevant only if UDPHS_EPTCFGx.EPT_TYPE = 0x0, 0x2 or 0x3.

For additional information, see UDPHS_EPTCTLx.

Name: UDPHS_EPTCTLDISx (DEFAULT_MODE)
Offset: 0x0108 + n*0x20 [n=0..6]
Reset: 
Property: Write-only

Bit 3130292827262524 
 SHRT_PCKT        
Access W 
Reset  
Bit 2322212019181716 
      BUSY_BANK   
Access W 
Reset  
Bit 15141312111098 
 NAK_OUTNAK_INSTALL_SNTRX_SETUPTXRDYTX_COMPLTRXRDY_TXKLERR_OVFLW 
Access WWWWWWWW 
Reset  
Bit 76543210 
    NYET_DISINTDIS_DMA AUTO_VALIDEPT_DISABL 
Access WWWW 
Reset  

Bit 31 – SHRT_PCKT Short Packet Interrupt Disable

For IN endpoints: Never automatically add a zero length packet at end of DMA transfer.

For OUT endpoints:

ValueDescription
0

No effect.

1

Disable Short Packet Interrupt.

Bit 18 – BUSY_BANK Busy Bank Interrupt Disable

ValueDescription
0

No effect.

1

Disable Busy Bank Interrupt.

Bit 15 – NAK_OUT NAKOUT Interrupt Disable

ValueDescription
0

No effect.

1

Disable NAKOUT Interrupt.

Bit 14 – NAK_IN NAKIN Interrupt Disable

ValueDescription
0

No effect.

1

Disable NAKIN Interrupt.

Bit 13 – STALL_SNT Stall Sent Interrupt Disable

ValueDescription
0

No effect.

1

Disable Stall Sent Interrupt.

Bit 12 – RX_SETUP Received SETUP Interrupt Disable

ValueDescription
0

No effect.

1

Disable RX_SETUP Interrupt.

Bit 11 – TXRDY TX Packet Ready Interrupt Disable

ValueDescription
0

No effect.

1

Disable TX Packet Ready/Transaction Error Interrupt.

Bit 10 – TX_COMPLT Transmitted IN Data Complete Interrupt Disable

ValueDescription
0

No effect.

1

Disable Transmitted IN Data Complete Interrupt.

Bit 9 – RXRDY_TXKL Received OUT Data Interrupt Disable

ValueDescription
0

No effect.

1

Disable Received OUT Data Interrupt.

Bit 8 – ERR_OVFLW Overflow Error Interrupt Disable

ValueDescription
0

No effect.

1

Disable Overflow Error Interrupt.

Bit 4 – NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints)

ValueDescription
0

No effect.

1

Let the hardware handle the handshake response for the High Speed Bulk OUT transfer.

Bit 3 – INTDIS_DMA Interrupts Disable DMA

ValueDescription
0

No effect.

1

Disable the “Interrupts Disable DMA”.

Bit 1 – AUTO_VALID Packet Auto-Valid Disable

ValueDescription
0

No effect.

1

Disable this bit to not automatically validate the current packet.

Bit 0 – EPT_DISABL Endpoint Disable

ValueDescription
0

No effect.

1

Disable endpoint.