37.9.2 XDMAC Global Configuration Register

Name: XDMAC_GCFG
Offset: 0x04
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
        BXKBEN 
Access R/W 
Reset 0 
Bit 76543210 
     CGDISIFCGDISFIFOCGDISPIPECGDISREG 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 8 – BXKBEN Boundary X Kilobyte Enable

ValueDescription
0

XDMAC generates a non-sequential attribute on the system bus when address crosses the 1-Kilobyte boundary with a burst access.

1

XDMAC does not generate a non-sequential attribute on the system bus when address crosses the 1-Kilobyte boundary with a burst access.

Bit 3 – CGDISIF Bus Interface Clock Gating Disable

ValueDescription
0

The automatic clock gating is enabled for the system bus interface.

1

The automatic clock gating is disabled for the system bus interface.

Bit 2 – CGDISFIFO FIFO Clock Gating Disable

ValueDescription
0

The automatic clock gating is enabled for the main FIFO.

1

The automatic clock gating is disabled for the main FIFO.

Bit 1 – CGDISPIPE Pipeline Clock Gating Disable

ValueDescription
0

The automatic clock gating is enabled for the main pipeline.

1

The automatic clock gating is disabled for the main pipeline.

Bit 0 – CGDISREG Configuration Registers Clock Gating Disable

ValueDescription
0 The automatic clock gating is enabled for the configuration registers.
1 The automatic clock gating is disabled for the configuration registers.