37.9.25 XDMAC Channel x Next Descriptor Control Register [x = 0..15]
| Name: | XDMAC_CNDC |
| Offset: | 0x6C + n*0x40 [n=0..15] |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| QOS[1:0] | NDVIEW[1:0] | NDDUP | NDSUP | NDE | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 6:5 – QOS[1:0] Channel Quality Of Service level
This field indicates the current quality of service level for the channel. Refer to the section “Bus Matrix (MATRIX)”.
Bits 4:3 – NDVIEW[1:0] Channel x Next Descriptor View
| Value | Name | Description |
|---|---|---|
| 0 | NDV0 | Next Descriptor View 0 |
| 1 | NDV1 | Next Descriptor View 1 |
| 2 | NDV2 | Next Descriptor View 2 |
| 3 | NDV3 | Next Descriptor View 3 |
Bit 2 – NDDUP Channel x Next Descriptor Destination Update
| Value | Name | Description |
|---|---|---|
| 0 | DST_PARAMS_UNCHANGED | Destination parameters remain unchanged. |
| 1 | DST_PARAMS_UPDATED | Destination parameters are updated when the descriptor is retrieved. |
Bit 1 – NDSUP Channel x Next Descriptor Source Update
| Value | Name | Description |
|---|---|---|
| 0 | SRC_PARAMS_UNCHANGED | Source parameters remain unchanged. |
| 1 | SRC_PARAMS_UPDATED | Source parameters are updated when the descriptor is retrieved. |
Bit 0 – NDE Channel x Next Descriptor Enable
| Value | Name | Description |
|---|---|---|
| 0 | DSCR_FETCH_DIS | Descriptor fetch is disabled. |
| 1 | DSCR_FETCH_EN | Descriptor fetch is enabled. |