54.5.6 SHA Interrupt Status Register
| Name: | SHA_ISR |
| Offset: | 0x1C |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SECE | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CHKST[3:0] | CHECKF | ||||||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| URAT[2:0] | URAD | ||||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WRDY | DATRDY | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bit 24 – SECE Security and/or Safety Event
| Value | Description |
|---|---|
| 0 | There is no report in SHA_WPSR. |
| 1 | There is a Security and/or Safety Event reported in SHA_WPSR. |
Bits 23:20 – CHKST[3:0] Check Status (cleared by writing SHA_CR.START or SHA_CR.SWRST or by reading SHA_IODATARx)
Value 5 indicates identical hash values (expected hash = hash result). Any other value indicates different hash values.
Bit 16 – CHECKF Check Done Status (cleared by writing SHA_CR.START or SHA_CR.SWRST or by reading SHA_IODATARx)
| Value | Description |
|---|---|
| 0 | Hash check has not been computed. |
| 1 | Hash check has been computed, status is available in the CHKST bits. |
Bits 14:12 – URAT[2:0] Unspecified Register Access Type (cleared by writing a 1 to SWRST bit in SHA_CR)
Only the last Unspecified Register Access Type is available through the URAT field.
| Value | Name |
|---|---|
| 0 | SHA_IDATAR0 to SHA_IDATAR15 written during data processing in DMA mode (URAD = 1 and URAT = 0 can occur only if DUALBUFF is cleared in SHA_MR) |
| 1 | Output Data Register read during data processing |
| 2 | SHA_MR written during data processing |
| 3 | Write-only register read access |
Bit 8 – URAD Unspecified Register Access Detection Status (cleared by writing a 1 to SHA_CR.SWRST)
| Value | Description |
|---|---|
| 0 | No unspecified register access has been detected since the last SWRST. |
| 1 | At least one unspecified register access has been detected since the last SWRST. |
Bit 4 – WRDY Input Data Register Write Ready
| Value | Description |
|---|---|
| 0 | SHA_IDATAR0 cannot be written |
| 1 | SHA_IDATAR0 can be written |
Bit 0 – DATRDY Data Ready (cleared by writing a 1 to bit SWRST or START in SHA_CR, or by reading SHA_IODATARx)
| Value | Description |
|---|---|
| 0 | Output data is not valid. |
| 1 | 512/1024-bit block process is completed. DATRDY is cleared when one of the following conditions is met: • Bit START in SHA_CR is set. • Bit SWRST in SHA_CR is set. • The hash result is read. |