54.5.9 SHA Input Data Register x

Name:	SHA_IDATARx
Offset:	0x40 + x*0x04 [x=0..15]
Reset:	–
Property:	Write-only


Bit	31	30	29	28	27	26	25	24
	IDATA[31:24]
Access	W	W	W	W	W	W	W	W
Reset	–	–	–	–	–	–	–	–


Bit	23	22	21	20	19	18	17	16
	IDATA[23:16]
Access	W	W	W	W	W	W	W	W
Reset	–	–	–	–	–	–	–	–


Bit	15	14	13	12	11	10	9	8
	IDATA[15:8]
Access	W	W	W	W	W	W	W	W
Reset	–	–	–	–	–	–	–	–


Bit	7	6	5	4	3	2	1	0
	IDATA[7:0]
Access	W	W	W	W	W	W	W	W
Reset	–	–	–	–	–	–	–	–

Bits 31:0 – IDATA[31:0] Input Data

32-bit Input Data registers load the data block used for hash processing.

These registers are write-only to prevent reading of input data by another application.

SHA_IDATAR0 corresponds to the first word of the block, SHA_IDATAR15 to the last word of the last block in case SHA algorithm is set to SHA1, SHA224, SHA256, or SHA_IODATAR15 to the last word of the block if SHA algorithm is SHA384 or SHA512 (see SHA Input/Output Data Register x).

SHA_IDATARx can be also written to configure the hash result of the previous fragment of a message when starting the processing of the next fragment when the SHA has processed another message in between fragments.