42.10 UHPHS Configure Flag Register
This register is in the auxiliary power well. It is only reset by hardware when the auxiliary power is initially applied or in response to a host controller reset.
| Name: | UHPHS_CONFIGFLAG |
| Offset: | 0x50 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CF | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – CF Configure Flag
Host software sets this bit as the last action in its process of configuring the Host Controller. This bit controls the default port-routing control logic. Bit values and side-effects are listed below.
| Value | Description |
|---|---|
| 0 | Port routing control logic default-routes each port to an implementation-dependent classic host controller (default value). |
| 1 | Port routing control logic default-routes all ports to this host controller. |