42.9 UHPHS Asynchronous List Address Register

This 32-bit register contains the address of the next asynchronous queue head to be executed. Bits [4:0] of this register cannot be modified by system software and will always return a zero when read. The memory structure referenced by this physical memory pointer is assumed to be 32-byte (cache line) aligned. This register must be written as a DWord. Byte writes produce undefined results.

Name:	UHPHS_ASYNCLISTADDR
Offset:	0x28
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	LPL[26:19]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	LPL[18:11]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	LPL[10:3]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	LPL[2:0]
Access	R/W	R/W	R/W
Reset	0	0	0

Bits 31:5 – LPL[26:0] Link Pointer Low

These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (QH).