42.3 UHPHS Host Controller Capability Parameters Register
These fields define capability parameters: Multiple Mode control (time-base bit functionality), addressing capability, etc.
| Name: | UHPHS_HCCPARAMS |
| Offset: | 0x08 |
| Reset: | 0x00000026 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EECP[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IST[3:0] | ASPC | PFLF | AC | ||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 1 | 0 | 1 | 1 | 0 | ||
Bits 15:8 – EECP[7:0] EHCI Extended Capabilities Pointer
Indicates the existence of a capabilities list. A value of 0 indicates no extended capabilities are implemented. A non-zero value in this register indicates the offset in the PCI configuration space of the first EHCI extended capability. The pointer value must be 64 or greater if implemented to maintain the consistency of the PCI header defined for this class of device.
Bits 7:4 – IST[3:0] Isochronous Scheduling Threshold
Indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. When bit [7] is 0, the value of the least significant three bits indicates the number of microframes a host controller can hold a set of isochronous data structures (one or more) before flushing the state. When bit [7] is set to 1, the host software assumes the host controller may cache an isochronous data structure for an entire frame.
Bit 2 – ASPC Asynchronous Schedule Park Capability
| Value | Description |
|---|---|
| 0 | Host controller does not supports the park feature for high-speed queue. |
| 1 | Host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule. |
Bit 1 – PFLF Programmable Frame List Flag
| Value | Description |
|---|---|
| 0 | System software must use a frame list length of 1024 elements with this host controller. The UHPHS_USBCMD register Frame List Size field is a read-only register and must be set to 0. |
| 1 | System software can specify and use a smaller frame list and configure the host controller via the UHPHS_USBCMD register Frame List Size field. The frame list must always be aligned on a 4-Kbyte page boundary. This requirement ensures that the frame list is always physically contiguous. |
Bit 0 – AC 64-bit Addressing Capability
This field documents the addressing range capability of this implementation. The value of this field determines whether software should use 32-bit or 64-bit data structures.
This information is not tightly coupled with the UHPHS_USBBASE address register mapping control. The 64-bit Addressing Capability bit indicates whether the host controller can generate 64-bit addresses as a host. The UHPHS_USBBASE register indicates the host controller only needs to decode 32-bit addresses as a client.
| Value | Description |
|---|---|
| 0 | Data structures using 32-bit address memory pointers |
| 1 | Data structures using 64-bit address memory pointers |