22.6.1 DBGU Control Register

Name: DBGU_CR
Offset: 0x0000
Reset: 
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     STTTORETTO RSTSTA 
Access WWW 
Reset  
Bit 76543210 
 TXDISTXENRXDISRXENRSTTXRSTRX   
Access WWWWWW 
Reset  

Bit 11 – STTTO Start Timeout

ValueDescription
0

No effect.

1

Starts waiting for a character before clocking the timeout counter. Resets status bit DBGU_SR.TIMEOUT.

Bit 10 – RETTO Rearm Timeout

ValueDescription
0

No effect.

1

Restarts timeout.

Bit 8 – RSTSTA Reset Status

ValueDescription
0

No effect.

1

Resets the status bits PARE, FRAME and OVRE in DBGU_SR.

Bit 7 – TXDIS Transmitter Disable

ValueDescription
0

No effect.

1

The transmitter is disabled. If a character is being processed and a character has been written in DBGU_THR and RSTTX is not set, both characters are completed before the transmitter is stopped.

Bit 6 – TXEN Transmitter Enable

ValueDescription
0

No effect.

1

The transmitter is enabled if TXDIS is 0.

Bit 5 – RXDIS Receiver Disable

ValueDescription
0

No effect.

1

The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped.

Bit 4 – RXEN Receiver Enable

ValueDescription
0

No effect.

1

The receiver is enabled if RXDIS is 0.

Bit 3 – RSTTX Reset Transmitter

ValueDescription
0

No effect.

1

The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted.

Bit 2 – RSTRX Reset Receiver

ValueDescription
0

No effect.

1

The receiver logic is reset and disabled. If a character is being received, the reception is aborted.