25.1.3 Host to Client Access
The table below describes how hosts and clients can be interconnected. Writing in a register or field not dedicated to a host or a client has no effect.
| Hosts | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Clients | ARM926 Instr. | ARM926 Data | XDMAC0 | XDMAC1 | SDMMC0 DMA | SDMMC1 DMA | UDPHS DMA | UHPHS EHCI | UHPHS OHCI | ISI DMA | EMAC0 DMA | EMAC1 DMA | OTPC Host I/F |
GFX2D | LCDC DMA | |
| 0 | SRAM0 | X | X | X | X | X | X | X | X | X | X | X | X | – | X | X |
| 1 | OTPC Client I/F | X | X | – | – | – | – | – | – | – | – | – | – | – | – | – |
| 2 |
UDPHS DPRAM UHPHS EHCI config. reg. UHPHS OHCI config. reg. |
X | X | – | – | – | – | – | – | – | – | – | – | – | – | – |
| 3 | EBI / MPDDRC / SDRAMC port 0 |
X | X | X | X | X | X | X | X | X | X | X | X | – | X | X |
| 4 | MPDDRC / SDRAMC port 1 |
X | – | X | – | X | – | X | – | – | – | X | – | – | – | – |
| 5 | MPDDRC / SDRAMC port 2 |
– | X | – | X | – | X | – | X | X | – | – | X | – | X | – |
| 6 | MPDDRC / SDRAMC port 3 |
– | – | – | – | – | – | – | – | – | X | – | – | – | – | X |
| 7 | Peripheral Bridge 0 | – | X | X | X | – | – | – | – | – | – | – | – | – | – | – |
| 8 | Peripheral Bridge 1 | – | X | X | X | – | – | – | – | – | – | – | – | – | – | – |
| 9 | QSPI | X | X | X | X | – | – | – | – | – | – | – | – | – | – | X |
| 10 | SDMMC0 config. reg. | – | X | – | – | – | – | – | – | – | – | – | – | – | – | – |
| 11 | SDMMC1 config. reg. | – | X | – | – | – | – | – | – | – | – | – | – | – | – | – |
| 12 | SRAM1 | X | X | – | – | – | – | – | – | – | – | – | – | X | – | – |