25.1.1 MATRIX Hosts

The MATRIX manages 15 hosts listed in the table below. Each host can perform an access, concurrently with others, to an available client. The MATRIX operates at the main system bus clock (MCK) frequency. Each host has its own decoder, which is defined specifically for each host. In order to simplify the addressing, all the hosts have the same decodings.

Table 25-1. List of MATRIX Hosts
Host No.Description
0ARM926 instruction
1ARM926 data
2, 3XDMA controller with QoS support
4SDMMC0 DMA
5SDMMC1 DMA
6USB high-speed device port (UDPHS) DMA
7USB high-speed host port (UHPHS) EHCI DMA
8USB high-speed host port (UHPHS) OHCI DMA
9ISI DMA
10EMAC0 DMA
11EMAC1 DMA
12OTP controller host interface
13GFX2D DMA
14LCDC DMA with QoS support