25.1.1 MATRIX Hosts
The MATRIX manages 15 hosts listed in the table below. Each host can perform an access, concurrently with others, to an available client. The MATRIX operates at the main system bus clock (MCK) frequency. Each host has its own decoder, which is defined specifically for each host. In order to simplify the addressing, all the hosts have the same decodings.
| Host No. | Description |
|---|---|
| 0 | ARM926 instruction |
| 1 | ARM926 data |
| 2, 3 | XDMA controller with QoS support |
| 4 | SDMMC0 DMA |
| 5 | SDMMC1 DMA |
| 6 | USB high-speed device port (UDPHS) DMA |
| 7 | USB high-speed host port (UHPHS) EHCI DMA |
| 8 | USB high-speed host port (UHPHS) OHCI DMA |
| 9 | ISI DMA |
| 10 | EMAC0 DMA |
| 11 | EMAC1 DMA |
| 12 | OTP controller host interface |
| 13 | GFX2D DMA |
| 14 | LCDC DMA with QoS support |