25.1.2 MATRIX Clients
The MATRIX manages the 13 clients listed in the table below. Each client has its own arbiter providing a dedicated arbitration per client.
| Client No. | Description |
|---|---|
| 0 | SRAM0 |
| 1 | OTPC client interface (ROM and OTP memory) |
| 2 | UDPHS dual port RAM |
| UHPHS OHCI configuration registers | |
| UHPHS EHCI configuration registers | |
| 3 | External Bus Interface / MPDDRC / SDRAMC port 0 with QoS support |
| 4 | MPDDRC / SDRAMC port 1(1) with QoS support |
| 5 | MPDDRC / SDRAMC port 2(1) with QoS support |
| 6 | MPDDRC / SDRAMC port 3(1) with QoS support |
| 7 | Peripheral bridge 0 |
| 8 | Peripheral bridge 1 |
| 9 | QSPI |
| 10 | SDMMC0 configuration registers |
| 11 | SDMMC1 configuration registers |
| 12 | SRAM1 |
Note:
- The multiport is available for the SDRAMC when the Multiplexed Address/Data Lines or the Address/Data/Command Lines mode is used. In standard SDRAM Connection mode, only port 0 is used. Refer to “Interface with Multiplexed Data/Address Lines and Data/Address/Command Lines”, in section SDRAM Controller (SDRAMC).