35.4.1 MLC/SLC Write Page Operation using PMECC

When an MLC write page operation is performed, the PMECC controller is configured with the NANDWR bit in the Configuration register (PMECC_CFG) set to one. When the NAND spare area contains file system information and redundancy (PMECCx), the spare area is error protected, then PMECC_CFG.SPAREEN is set to ‘1’. When the NAND spare area contains only redundancy information, SPAREEN is set to ‘0’.

When the write page operation is terminated, the user writes the redundancy in the NAND spare area. This operation can be done with DMA assistance.

Table 35-1. Relevant Redundancy Registers
BCH_ERR FieldSector Size Set to 512 BytesSector Size Set to 1024 Bytes
0PMECC_ECC0PMECC_ECC0
1PMECC_ECC0, PMECC_ECC1PMECC_ECC0, PMECC_ECC1
2PMECC_ECC0, PMECC_ECC1, PMECC_ECC2, PMECC_ECC3PMECC_ECC0, PMECC_ECC1, PMECC_ECC2, PMECC_ECC3
3PMECC_ECC0, PMECC_ECC1, PMECC_ECC2, PMECC_ECC3, PMECC_ECC4, PMECC_ECC5, PMECC_ECC6PMECC_ECC0, PMECC_ECC1, PMECC_ECC2, PMECC_ECC3, PMECC_ECC4, PMECC_ECC5, PMECC_ECC6
4PMECC_ECC0, PMECC_ECC1, PMECC_ECC2, PMECC_ECC3, PMECC_ECC4, PMECC_ECC5, PMECC_ECC6, PMECC_ECC7, PMECC_ECC8, PMECC_ECC9PMECC_ECC0, PMECC_ECC1, PMECC_ECC2, PMECC_ECC3, PMECC_ECC4, PMECC_ECC5, PMECC_ECC6, PMECC_ECC7, PMECC_ECC8, PMECC_ECC9, PMECC_ECC10
Table 35-2. Number of Relevant ECC Bytes per Sector, Copied from LSbyte to MSbyte
BCH_ERR FieldSector Size Set to 512 BytesSector Size Set to 1024 Bytes
04 bytes4 bytes
17 bytes7 bytes
213 bytes14 bytes
320 bytes21 bytes
439 bytes42 bytes